FAQ

Hardware IP cores are IP (Intellectual Property) cores that are used to program (configure) hardware accelerators like FPGA devices. The IP cores can be in several forms like source code, netlist or configuration files.

InAccel provides any required form of IP cores (source code (HLS or OpenCL), netlist or configuration file) depending on the application's requirements.

Yes. Amazon and Accelize allow users to rent FPGA modules as a service through Amazon AWS. The user can rent the FPGA resources per hour and then can instantiate the IP cores for the configuration of the FPGAs. The pricing model for the use of the IP cores is similar to Amazon AWS (cost is allocated per hour).

The cost of the IP cores depends on the format that is required. The purchase of the source code allow users to modify the core based on the application requirements and can be used in many projects but it has higher initial cost. The use of IP cores as a service (e.g. through Amazon AWS) allow users to pay as much as the IP core is used (pay-as-you-go).

InAccel provides all the required APIs for the seamless integration of the IP cores for your application. The current supported APIs include C/C++, Java, Python, and Scala. InAccel also provides the required libraries for the integration of the IP cores from widely-used programming frameworks like Apache Spark and Mahout. These APIs allow integration of the IP cores without any changes of your source code.

InAccel provides the required library, compatible with Spark, that allow users to utilize the IP cores without any changes in the Spark application. The only change that is required is the replacement of the MLlib library with the InAccel library for the use of the IP core.

No. When the users rent the FPGA units, they also have access to the host device that is communicating with the FPGA. That means, that the users can run their applications in the host processors that is also located in the same resources as the FPGA machine. However, the users can also rent additional typical compute units and to communicate with the FPGAs.

The speedup of the accelerator (IP core) is evaluated compared to a single thread contemporary processor (e.g. C4 compute unit from Amazon AWS).

Hardware IP cores have lower flexibility compared to software as they are made to map directly into hardware circuits. That means that if the user need to change some of the parameters of the code a new design (core) may be required. However, most of the cores support a maximum number of parameters that satisfy most of the applications. For example, the LR (Logistic Regression) IP core supports up to 24 classes.

You can find here the license agreement for the InAccel IP cores.