Last month, Xilinx™, a leader in FPGA-based hardware accelerators released the new EDA tool called Vitis™ that allow design engineers to develop accelerators for the FPGA-based boards like Alveo and Zynq platform from high-level languages like OpenCL and HLS (High-level Synthesis). At the same time, Xilinx released a large open-source suite of libraries for widely used applications like compression, encryption, financial, linear algebra and ML. The libraries are provided as open-source in HLS that can be synthesized (compiled) with the Vitis™ tool to the Alveo™ board. However, software engineers usually have to invoke the libraries from OpenCL and some time this limits the widespread adoption. Also, software engineers have to deal in the host code with the bitstreams (FPGA configuration files), buffer management, and queues for the communication with the accelerators. Finally, current frameworks do not allow the utilization of the accelerators from multiple threads, processes or applications in an efficient way.
In order to allow the widespread adoption of the FPGA-based accelerators, software users need to be able to deploy, manage and scale their application as easy as it is currently done using CPUs and GPUs. The users do not need to know about bitstream or buffer allocation. Users need to be able to invoke the functions that they want to accelerate from multiple threads, multiple processes or multiple applications.
InAccel, announced today the new version of the FPGA resource manager that makes easier than ever the utilization of FPGAs using the new Vitis™ Libraries. InAccel has decoupled the use of the FPGA configuration files (called bitstreams) from the source code of the host making much easier the utilization of the FPGAs. InAccel has pre-compiled the new Vitis™ libraries for the Xilinx™ Alveo™ boards (U50, U200, U250, and U280) for the most widely used applications (financial, encryption, compression, machine learning, linear algebra) and it is now hosted on a separate repository (i.e. artifactory).
The main advantage of this approach is that InAccel’s Coral FPGA resource manager (orchestrator) abstracts away the hardware resources (FPGAs) available on a server, making easier than ever the utilization of the Xilinx Alveo boards without even using the Vitis EDA tool. The FPGA resource manager allows that way:
- Invoking of the accelerators from C/C++, Java and Python. No need for OpenCL. Zero code changes as the accelerator functions overload the software functions.
- Invoking of the accelerators from multiple threads, processes, applications seamless. No need for synchronization between the applications that need to access the accelerators.
- Instant scaling to multiple FPGAs on the same servers. No need to manually dispatch the tasks to the cluster of FPGAs.
- Instant scaling to multiple Alveo-based servers using the Kubernetes plug-in.
You can check an example of the new paradigm of using the Vitis libraries with InAccel’s FPGA resource manager here.
You can check InAccel repository of the Hardware accelerators here.
Xilinx, Vitis and Alveo are trademarks of Xilinx Corporation or its subsidiaries in the U.S. and/or other countries.
InAccel is a trademark of InAccel Corporation or its subsidiaries in the U.S. and/or other countries.